18.6 Cache Test Mode Protocol

Auto-Increment Read Protocol

A cache test mode auto-increment read operation reads a selected RAM array. The read address is obtained by incrementing the previous access address, and the read way is obtained from the previous access way.

If an overflow occurs when incrementing the previous access address, the address wraps to 0, and the way is toggled.

The external agent issues an auto-increment read command by:

 After a read latency of 15 PClk cycles, the processor provides the read response by:

 In the following SysClk cycle, the processor reverts to Slave state.

Auto-increment reads have a repeat rate of 17 PClk cycles.

Figure 18-6 depicts two cache test mode auto-increment reads.



Figure 18-6 Cache Test Mode Auto-Increment Read Protocol

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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